1. Field of the Invention
The present invention relates to one-dimensional and two-dimensional discrete cosine transformation processor, and in particular relates to one-dimensional discrete cosine transformation processor whose block size in 8 sample and two-dimensional discrete cosine transformation processor whose block size is 8.times.8 sample.
2. Description of the Prior Art
Conventionally, digital signals for image data are coded with utilizing discrete cosine transformation. FIGS. 7 and 8 show examples of multiply-accumulate operators used in processors for the discrete cosine transformation.
FIG. 7 gives the configuration of a conventional discrete cosine transformation processor with a single product-sum operator. This discrete cosine transformation processor divides the input data into a plurality of blocks with several data so as to transform the blocks one by one. Suppose here that one block has eight data.
A discrete cosine transformation processor comprises a selection circuit 401, a coefficient generator 410, a multiply-accumulate operator 420 and an output terminal 430. The selection circuit 401 receives eight input data (f0 to f7) and supply them to the multiply-accumulate operator 420. The coefficient generator 410 adds a sign (+or -) to one of coefficients P1 to P7 before supplying it to the multiply-accumulate operator 420. Values given next to the coefficient generator 410 in the figure indicate coefficients with signs to be selected every clock. For example, "-4" means that "-P4" is to be output.
The multiply-accumulate operator 420 comprises a multiplier 441, an adder 442 and a latch circuit 443. To the multiplier 441, signals are supplied from the selection circuit 401 and the coefficient generator 410. The output of the multiplier 441 is sent to the adder 442, and the output of the adder 442 to the latch circuit 443. The output of the latch circuit 443 is provided to the adder 442 and the output terminal 430.
The operation of a conventional discrete cosine transformation processor with the configuration as above is now described briefly.
The selection circuit 401 supplies input data f0, f1, f2, f3, f4, f5, f6 and f7 in this order to the multiplier 441 with giving one data for each clock. The coefficient generator 410 selects one of the coefficients P1 to P7, adds a sign to it and sends it as a transformation coefficient to the multiplication device 441. The multiplier 441 calculates the product of the input data (one of f0-f7) and the transformation coefficient (one of P1-P7) and supplies it to the multiply-accumulate operator 420. At the multiply-accumulate operator 420, the signal from the multiplier 441 is accumulated with the adder 442 and the latch circuit 443 and sent to the output terminal 430. Thus, discrete cosine transformation coefficients F0 to F7 are in this order output from the output terminal 430 every eight clocks.
In the figure, "*" marks insignificant values on the way of calculation.
Inverse discrete cosine transformation operation is to determine a inverse cosine transformation coefficient (input data) based on a discrete cosine transformation coefficient. This inverse operation can be executed with the same procedure as in the above discrete cosine transformation operation except for the order of the coefficients selected at the coefficient generator 410.
The above discrete cosine transformation processor requires eight clocks for determination of a single discrete cosine transformation coefficient (one of F0 to F7). Thus, 64 clocks are required if eight discrete cosine transformation coefficients are to be determined.
FIG. 8 shows another conventional discrete cosine transformation processor with eight multiply-accumulate operators. This discrete cosine transformation processor comprises eight multiply-accumulate operators 470 to 477, eight coefficient generators 460 to 467 which supply transformation coefficients (P1 to P7) to the above multiply-accumulate operators 470 to 477, and a selection circuit 451 which supplies input data (f0 to f7) to the multiply-accumulate operators 470 to 477.
In the figure, the values given on the left of the coefficient generators 460 to 467 are coefficients with signs to be selected every clock. The values before the slashes are for ordinary discrete cosine transformation operation and those after the slashes are for inverse discrete cosine transformation operation. Meaning of the values themselves are the same as in the above discrete cosine transformation processor (FIG. 7).
With a discrete cosine transformation processor with the above configuration, eight pairs of coefficient generators 460 to 467 and multiply-accumulate 470 to 477 enable determination of eight discrete cosine transformation coefficients in eight clocks (one discrete cosine transformation coefficient in one clock), resulting in rapid processing at a speed eight times higher than that for the discrete cosine transformation processor in FIG. 7.
As described above, the conventional discrete cosine transformation processor as shown in FIG. 7 uses a single multiply-accumulate operator 420 for operation and requires as many as 64 clocks to process a single block (with eight coefficients). This slow processing speed is a drawback of this processor.
In case of a discrete cosine transformation processor as shown in FIG. 8, it certainly enables processing at a speed eight times higher than that for the processor in FIG. 7, but it requires a large amount of hardware devices. For example, when a processor using a single multiply-accumulate operator requires a circuit with 5,000 gates, this processor with eight times higher processing speed needs a circuit with 40,000 gates.